1. Field of the Invention
The present invention relates to a leadframe which includes offsets that extend transversely from a major plane thereof. Particularly, the offsets of the leadframe extend from the leadframe at a non-perpendicular angle. More particularly, the offsets of the present invention reduce stress in the package by optimally positioning the die and, thus, prevent or reduce warpage, bending, or skewing of a packaged semiconductor device into which the offsets are incorporated.
2. Background of Related Art
With reference to FIG. 1, a conventional packaged semiconductor device 10 typically includes a semiconductor device 14, which is also referred to as a die, leads 26 operatively connected to the semiconductor device, and a filled-polymer packaging material 16, which is also typically referred to as an xe2x80x9cencapsulant.xe2x80x9d Packaging material 16 defines a package 18 that surrounds at least a portion of each of semiconductor device 14 and its associated leads 26.
Various types of leadframes have been employed in the packaging of semiconductor devices. FIG. 1 illustrates an exemplary, conventional leadframe 20, which includes a die paddle 22, a tie bar 24, and a plurality of leads 26 extending at least partially outwardly toward a frame (not shown), or periphery, of leadframe 20. Typically, the leads 26 extend through the packaging material 16 of the packaged semiconductor device 10 and externally thereof in order to facilitate the establishment of an electrical connection between the leads and a carrier substrate such as a printed circuit board (PCB). Leadframes that do not include a die paddle, which are typically referred to as xe2x80x9cpaddle-lessxe2x80x9d leadframes, such as xe2x80x9cleadsover-chipxe2x80x9d (LOC) configured leadframes and xe2x80x9cleads-under-chipxe2x80x9d (LUC) configured leadframes, are also employed in conventional packaged semiconductor devices.
The tendency of a packaged semiconductor device to warp, bend, or skew when subjected to temperature changes or high temperatures, such as during the solidification of the molten packaging material following encapsulation or during the operation of the finished packaged semiconductor device, has long been a concern to designers and manufacturers of packaged semiconductor devices (xe2x80x9cdicexe2x80x9d). As the die, packaging material, leads and other packaged semiconductor device components undergo temperature changes or are subjected to high temperatures, the diverse coefficients of thermal expansion of these various components may cause the packaged semiconductor device of which they are a part to expand, warp, bend, skew, or otherwise distort. Typically, the higher the temperature to which the die, packaging material, leads and other packaged semiconductor device components are subjected, the greater the tendency toward warpage, bending, or other shape changes in the package. With the everincreasing circuit densities and reduced sizes of state of the art semiconductor devices, the operating temperatures of many such devices are also ever-increasing. Thus, state of the art packaged semiconductor devices have an increased tendency for warpage, bending, skewing and other dimensional distortions.
Some packaged semiconductor devices include stiffening elements to counteract such warpage, bending, or skewing. Exemplary packaged semiconductor devices that include stiffening elements are disclosed in U.S. Pat. No. 5,644,161 (the xe2x80x9c""161 patent), which issued to Carmen D. Burns on Jul. 1, 1997, and U.S. Pat. No. 5,369,058 (the xe2x80x9c""058 patentxe2x80x9d), which issued to Carmen D. Burns et al. on Nov. 29, 1994. The stiffening elements of the ""161 and ""058 patents are warp-resistant metal layers that are disposed proximate both of the major surfaces of the semiconductor device and are substantially coextensive with the major surfaces. Such stiffening elements are, however, somewhat undesirable from the standpoint that they are separate from the leadframe and, therefore, additional assembly steps are required during packaging of the semiconductor device. Thus, packaging costs and the likelihood of damaging the semiconductor device during packaging are increased. Since these stiffening elements are additional to the leadframe, they may also undesirably increase the size of the packaged semiconductor device. Moreover, the stiffening elements of the ""161 and ""058 patents are substantially parallel to the major plane of the leadframe of the packaged semiconductor device, and thus are not likely to provide any added heat sink properties to the packaged semiconductor device. Therefore, these stiffening elements do not counteract warpage, bending, or skewing of the packaged semiconductor device in directions that are substantially parallel to a plane in which a substantial portion of the leadframe is located.
During many conventional packaging processes, such as transfer molding and injection molding processes, a semiconductor device may be displaced within a cavity of a mold and the leads bent or disassociated from the semiconductor device by the hydraulic forces of the molten packaging material during its introduction into the mold cavity. Thus, the orientation of the semiconductor device relative to the exterior surface of the package may be altered. Such displacement of the semiconductor device may force the semiconductor device against an inner surface of the cavity, which could damage the semiconductor device or, at the least, compromise the integrity of the package. Non-optimal positioning of a semiconductor device within a package also changes the designed balance of the package, which causes residual stresses within the package.
U.S. Pat. No. 5,570,272 (the xe2x80x9c""272 patentxe2x80x9d), which issued to Patrick Variot on Oct. 29, 1996, and U.S. Pat. No. 5,692,296 (the xe2x80x9c""296 patentxe2x80x9d), which issued to Patrick Variot on Dec. 2, 1997, each disclose a leadframe that has been configured to counteract displacement of the leadframe-semiconductor device assembly within a mold during the introduction of a packaging material into the cavity thereof and which includes a heat sink that is exposed to an outer surface of the package. The leadframe of the ""272 and ""296 patents includes tie bars that extend perpendicularly upward relative to the plane of the leadframe a sufficient distance that, when placed within a cavity of a mold, the tie bars will force a heat sink that is disposed beneath the leadframe into contact with an inner surface of the cavity. As the leadframe is positioned within a cavity of a mold, the tie bars abut an inner surface of the cavity and force the leadframe and heat sink against an opposite inner surface of the cavity in order to secure the leadframe within the cavity. Thus, as molten packaging material is introduced into the cavity, the perpendicularly extending tie bars resist any tendency of the hydraulic force of the molten packaging material to xe2x80x9cliftxe2x80x9d the assembly in the mold cavity, holding the leadframe and the semiconductor device carried thereon in place as the packaging material is introduced into the cavity, and preventing packaging material from covering the bottom surface of the heat sink.
The perpendicularly extending tie bars of the leadframe of the ""272 and ""296 patents are, however, somewhat undesirable because, as a mold is closed around that leadframe, the tie bar extensions contact the inner surface of the mold cavity, and may exert force thereagainst, which may scratch or otherwise damage the wall surfaces of the cavity. Damaging the interior surfaces of the mold cavity may cause aesthetic changes to the finished packaged semiconductor device, may hinder release of the package from the mold, and may adversely affect the ability of conventional transfer equipment to properly handle the packaged semiconductor device during subsequent assembly or testing steps, which may cause such equipment to drop or otherwise mishandle the packaged semiconductor device, and thereby increase failure rates. Furthermore, since the tie bars extend perpendicularly from the leadframe, as force is applied to an end of one of the tie bars, the tie bar may flex or bend unpredictably under the longitudinal loading and displace the semiconductor device within the cavity. As noted previously, such displacement of the leadframe within the cavity offsets the leadframe within the finished packaged semiconductor device, which may affect the dimensions, the mechanical balance, and the mechanical and electrical reliability of the packaged semiconductor device. When the packaging material hardens, if these tie bars have been previously flexed under force of the closed mold, upon release of the package from the mold, the tie bars may exert force on the packaging material, which may cause bowing, warpage, bending, or skewing of the packaged semiconductor device, or cause the packaging material to crack or otherwise separate.
The leadframe that is disclosed in the ""272 and ""296 patents is further undesirable since the perpendicularly extending offsets thereof prevent compact stacking of such leadframes for storage. Thus, these leadframes consume excessive space in storage and in the equipment that feeds these leadframes into molding equipment relative to the amount of space consumed by conventional leadframes that may be compactly stacked.
Thus, a leadframe is needed that resists warpage, bending, skewing and other distortions when incorporated into a packaged semiconductor device, and which prevents displacement of an associated semiconductor device within a mold cavity during packaging processes without damaging interior surfaces of a mold cavity. There is a further need for a leadframe that may be stacked and stored in a relatively compact manner.
A leadframe of the present invention may be of a conventional, LOC, LUC, or any other leadframe configuration that is employed in the art. The leadframe according to the present invention includes a plurality of leads extending inwardly therefrom. The leadframe of the present invention also includes a plurality of offsets that extend transversely and nonperpendicularly therefrom relative to a plane upon which a substantial portion of a die mounting region of the leadframe lies, which may be characterized as the xe2x80x9cmajor planexe2x80x9d of the leadframe. The offsets preferably extend from the leadframe at an angle of about 45 degrees or less to this major plane.
In a first variation of the leadframe of the present invention, each of the offsets extends from the same side of the leadframe. In a second variation, offsets extend from both sides of the leadframe. Offsets may be specially added to the leadframe to extend from any portion thereof, or may be incorporated into the structure of an existing element of the leadframe, such as a lead, tie bar, bus bar, or die paddle thereof,
Accordingly, the present invention also includes methods of designing a leadframe with one or more offsets. In designing the leadframe of the present invention, various factors may be considered in determining the number, location, direction of extension and length of the offsets. Such factors include, without limitation, the predicted warpage tendencies of the particular package-leadframe-semiconductor device combination and the desired manner in which packaging material enters and fills a cavity of a mold to surround the leadframe-semiconductor device assembly disposed within the mold cavity.
A method of packaging a semiconductor device in association with the leadframe of the present invention includes operatively attaching the semiconductor device to the leadframe, and positioning the leadframe-semiconductor device assembly in a cavity of a mold, such that selected ones of the offsets abut or are proximate an interior surface of the cavity. As a molten packaging material is injected into the mold cavity, the offsets resist the force of the flow of the molten packaging material traversing the cavity in order to maintain the position of the leadframe relative to the cavity.
Packaged semiconductor devices that are formed in accordance with the method of packaging are also within the scope of the present invention. The packaged semiconductor device includes the leads and offsets of the inventive leadframe, a semiconductor device operatively attached to the leads, and a molded package disposed about at least a portion of the leadframe-semiconductor device assembly. The offsets extend substantially through the package from the leadframe major plane to a location proximate an exterior surface thereof. An offset may also extend to the exterior of the package such that a portion of the offset is flush with an edge thereof exposed to the package exterior.
Other advantages of the present invention will become apparent to those of ordinary skill in the relevant art through a consideration of the appended drawings and the ensuing description.